1. Field of the Invention
The present invention relates to a DRAM cell capacitor and, more particularly, to a method for fabricating a DRAM cell capacitor having HemiSpherical Grain (HSG) silicon on a storage node, wherein a bottom portion thereof has no HSG so as to prevent electrical bridges between adjacent storage nodes.
2. Description of the Related Art
Recent advances in the miniaturization of integrated circuit devices, such as high density DRAMs, have reduced the wafer area available for each individual memory cell. Yet, even as the footprint (an area of a silicon wafer allotted for individual memory cells) shrinks, the storage node must maintain a certain minimum charge storage capacity, determined by design and operational parameters to ensure reliable operation of memory cell. It is thus increasingly important that capacitors have a high charge storage capacity per unit area of the wafer. Accordingly, several techniques have been recently developed to increase the total charge capacity of the cell capacitor without significantly affecting the wafer area occupied by the cell.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. An inter-electrode dielectric material is deposited between two conductive layers that form the capacitor plates or electrodes. The amount of charge stored on the capacitor is proportional to the capacitance. C=.di-elect cons. .di-elect cons..sub.0 A/d, where .di-elect cons. is the dielectric constant of the capacitor dielectric, .di-elect cons..sub.0 is vacuum permittivity, A is the electrode area, and d represents the spacing between electrodes. Some techniques for increasing capacitance include the use of new materials having high dielectric constants.
Other techniques have focused on increasing the effective surface area ("A") of the electrodes by modifying the surface morphology of the polysilicon storage electrode itself by engraving or controlling the nucleation and growth condition of polysilicon. An HSG polysilicon layer can be deposited over a storage node to increase a surface area and capacitance.
U.S. Pat. No. 5,623,243 by Watanabe et al. entitled as "SEMICONDUCTOR DEVICE HAVING POLYCRYSTALLINE SILICON LAYER WITH UNEVEN SURFACE DEFINED BY HEMISPHERICAL OR MUSHROOM LIKE SHAPE SILICON GRAIN" is incorporated herein by reference. U.S. Pat. No. 5,741,734 by Young Jung Lee, U.S. Pat. No. 5,634,974 by Ronald A et al., U.S. Pat. No. 5,798,298 by Kiyoshi Mori et al., the disclosures of which are incorporated by reference herein, discloses capacitors with rough surface morphology.
Conventional methods for fabricating a DRAM cell capacitor with HSG silicon are described as follows: depositing a storage electrode layer, patterning the storage electrode layer to form a storage electrode; forming an HSG silicon layer; forming a dielectric layer such as Ta.sub.2 O.sub.5 ; forming a plate electrode layer, and patterning the plate electrode layer.
If a design rule of 0.15 micrometers or less is used, a polysilicon layer for the storage node must be formed thick to obtain a desired capacitance in a given cell area. The patterning of such thick polysilicon layer is very difficult and causing a problem associated with slope etching. As schematically illustrated in FIG. 1, an electrical bridge at the bottom portion of the patterned storage node can be generated due to a polysilicon tail (see reference number 22) caused by slope etching. Furthermore, when HSG silicon is formed on the patterned polysilicon layer (i.e., storage node), aforementioned electrical bridge can be generated extensively (see reference number 23).
Accordingly, overetching is required to remove the polysilicon tail. Such overetching can make the neck portion of the resulting storage node thin (see reference number 24 of FIG. 2) when misalignmentcan occurs. In severe cases, the storage node may fall down.
Accordingly, there is a strong need for a method for fabricating a DRAM cell capacitor with increased surface areas without causing an electrical bridge and falling down of the storage node.